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Texas Instruments /MSP432P4011 /PCM /PCMCTL1

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Interpret as PCMCTL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LOCKLPM5_0)LOCKLPM5 0 (LOCKBKUP_0)LOCKBKUP 0 (FORCE_LPM_ENTRY_0)FORCE_LPM_ENTRY 0 (PMR_BUSY)PMR_BUSY 0PCMKEY

LOCKBKUP=LOCKBKUP_0, LOCKLPM5=LOCKLPM5_0, FORCE_LPM_ENTRY=FORCE_LPM_ENTRY_0

Description

Control 1 Register

Fields

LOCKLPM5

Lock LPM5

0 (LOCKLPM5_0): LPMx.5 configuration defaults to reset condition

1 (LOCKLPM5_1): LPMx.5 configuration remains locked during LPMx.5 entry and exit
LOCKBKUP

Lock Backup

0 (LOCKBKUP_0): Backup domain configuration defaults to reset condition

1 (LOCKBKUP_1): Backup domain configuration remains locked during LPM3.5 entry and exit
FORCE_LPM_ENTRY

Force LPM entry

0 (FORCE_LPM_ENTRY_0): PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry.

1 (FORCE_LPM_ENTRY_1): PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off.
PMR_BUSY

Power mode request busy flag
PCMKEY

PCM key

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data